隨著 AI 運算對高速、低功耗資料傳輸需求的日益升高，共同封裝光學（Co-Packaged Optics, CPO）技術正逐步成為下一代資料中心互連架構的關鍵發展方向。同時，NVIDIA 與 Broadcom 等國際大廠相繼投入 CPO 技術研發與產品開發，2026 年有望迎來 CPO 元年。
時代基金會將於 1月21日 (三) 邀請 MIT Anu Agarwal 博士，以「Scale the Package – The Semiconductor Package is the 21st Century Transistor」為題，分享如何透過被動式組裝的 chip-to-chip 與 chip-to-fiber 高效耦合技術，降低光學元件整合門檻，並加速 CPO 技術導入先進封裝應用。歡迎踴躍參與（報名連結）。
【講者介紹】
Anu Agarwal 博士現任 MIT 微光子學中心與材料研究實驗室 (MIT Microphotonics Center and Materials Research Laboratory) 首席研究科學家。她於電子光子晶片 (electronic-photonic chips) 領域深耕多年，研究範疇涵蓋多晶矽波導 (polysilicon waveguides)、發光二極體 (LED) 、耦合器 (couplers) 和光電探測器(photodetectors)，致力於以矽 CMOS 製程整合主動與被動光學元件。Agarwal 博士亦專注開發中紅外光 (MIR) 的材料與元件，打造可整合的微光子平台，推動晶片成像與生化感測等應用。
Agarwal 博士自 2018 年領導 MIT.nano 的 LEAP 計畫， 透過 Integrated Photonic Systems Roadmap – International (IPSR-I) 建立光子感測器藍圖，識別光子感測器材料、元件和系統間的技術差距。同時，Agarwal 博士也是 MIT 微光子學中心 Electronic-Photonic Packaging (EPP) 主任，探索創新光子測試和封裝解決方案，推動高效微晶片製造模式。2022 年，Agarwal 博士獲選為 Optica Fellow，曾發表超過 250 篇學術期刊，並擁有 21 項專利。
【Epoch-MIT ILP Speech】
時間：2026年1月21日 10:00 – 11:30（三）(台北時間)
地點：Garage+ 台北市中山北路二段96號後棟9樓
報名： 報名連結
備註：時代基金會保留變更活動及審核參加者資格之權利
演講題目：Scale the Package – The Semiconductor Package is the 21st Century Transistor
演講大綱：
Energy consumption is at an all-time high in data centers. Enhanced microchip functionality for next generation applications such as AI, 6G, LiDAR etc. can no longer depend solely on shrinking the dimensions of a transistor. The semiconductor package is the 21st century transistor and this must be scaled to obtain high performance systems.
Generative-AI (Gen-AI) models require massive and rapid data movement between thousands of interconnected processors (GPUs/XPUs) and memory systems. Traditional electrical interconnects, which rely on long traces on a circuit board and power-hungry pluggable optical modules, have reached their physical and energy limits. The electrical signals degrade over distance, requiring additional components like digital signal processors (DSPs) and retimers, which consume significant power and add latency.
Co-packaged optics (CPO) is essential for this recent Gen-AI-driven revolution because it directly addresses the critical bottlenecks of power consumption, bandwidth density, and latency that are crippling traditional data center architectures. CPO overcomes these limitations by integrating optical engines directly onto the same package as the processing chip (ASIC). This dramatically shortens the electrical path from centimeters to mere millimeters, allowing data to be converted to light and transmitted much more efficiently.
Through FUTUR-IC, a global research alliance, we are enabling CPO within microchip systems, with high-performance, passively assembled chip-to-chip and chip-to-fiber couplers which employ graded-index and evanescent structures, fabricated using standard complementary metal-oxide-semiconductor foundry processes.
The urgency to align microchip system performance scaling with a commercially viable manufacturing value chain dominates business and technology decisions today, as the solutions are expected to power the next 40 years of progress for the semiconductor industry.