Ad-STAC Forum--Latest R&D Results in 3D IC Integration
2013-06-17
The 2013 IEEE Electronic & Components Technology Conference (ECTC) was held from May 28-31, 2013 in Las Vegas, Nevada, USA. There were more than 85 3D IC integration papers and Dr. John H. Lau has been digesting their presentations at the conference and reading their papers from the Proceedings. The objective of this half-day lecture is to systematically share with you the latest research and developments in design, materials, process, test, characterization, and reliability of 3D IC integration.

※主辦單位:工業技術研究院電子與光電研究所
※協辦單位:先進堆疊系統與應用研發聯盟(Ad-STAC)
※日期:102年6月27日(星期四)
※報到時間:08:30~09:00
※上課時間:09:00~12:00
※地點:工研院中興院區51館4樓國際會議廳
(新竹縣竹東鎮中興路四段195號)
※講師:劉漢誠博士(Dr. John H. Lau)

John H. Lau has been an ITRI Fellow since January 2010. Prior to that, he was a Senior Scientist/MTS at HPL/Agilent in California, US for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has authored more than 415 peer-reviewed publications, more than 25 issued and pending US patents, given more than 280 lectures/workshops/keynotes worldwide, and authored 17 textbooks on TSV for 3D IC integration, 3D MEMS packaging, wafer-level flip chip and reliability. John earned his PhD degree from the University of Illinois, three master degrees in North America, and a BE degree from NTU. John received many awards, e.g., the 2013 IEEE Components Packaging and Manufacturing Technology Field Award. He is an elected ASME Fellow and has been an IEEE Fellow since 1994.

Lecture Outlines
1.IMEC’s finding on the impact of post-plating anneal and TSV dimensions on Cu pumping
2.RPI/SEMATECH’s backside TSV protrusion induced by thermal shock and thermal cycling
3.RTI’s fabrication of TSV interposers with multilevel frontside and backside RDLs
4.Dai Nippon Printing’s TSV interposer with redistribution layers on both sides
5.ITRI’s design, materials, and process of 3D TSV/RDL interposer with chips on both sides
6.IBM’s thermally enhanced pre-applied underfills for 3D IC integration
7.IMEC’s GHz scanning acoustic microscopy for TSV void detection
8.ASE’s microbump bondability design guidelines for 3D IC integration
9.IMEC’s key elements for <50μm pitch microbump processes
10.Kyushu University’s 3D IC integration with ultrasonic bonding of Au cone bumps
11.Chipbond’s Au and pillar bumps for 3D chip stacking
12.Waseda University/NIMS/IBM/NCI’s Au-Au bonding using planar adhesive for 3D IC integration
13.Dow Corning’s low cost, room temperature debondable spin-on temporary bonding solution
14.IMEC’s thin-wafer handling: from WaferBOND HT-10.10 to ZoneBOND materials
15.Leti’s thin-wafer handling comparison between WSS and ZoneBOND for thin interposers
16.SPIL’s TSV backside via reveal process
17.SHINKO/Leti’s warpage control of 2.5D TSV interposer
18.NIST’s x-ray micro-beam diffraction determination of stresses in Cu TSVs
19.University of Alaska’s quick assessment of the thermomechanical stresses of Cu-filled TSVs
20.Hynix’s reliability studies on microbumps for 3D IC integration
21.Xilinx’s assembly qualification and reliability evaluations of 2.5D FPGA with HiCTE ceramic
22.TSMC’s reliability (experimental) characterization of CoWoS 2.5D IC integration technology
23.Xilinx/TSMC’s reliability (simulation) evaluations of CoWoS 2.5D IC integration technology
24.IMEC’s thermal comparison between Si interposer and 3D stacking packaging concepts
25.Leti’s TSV last process for hybrid pixel detectors
26.Qualcomm/Amkor’s wide I/O DRAM assembly development
27.GIT’s Cu microwire arrays for Si/glass/low-CTE-organic interposers to PCB SMT interconnections
28.STMicroelectronics/Leti’s 3D integration of CMOS image sensor with coprocessor using TSVs
29.IZM’s MEMS components with TSVs
30.IBM’s TSV process control in manufacturing for SiGe power amplifiers
31.Leti’s 3D Si interposer for millimeter wave up to 67 GHz applications